Field of the Invention
The invention relates to an integratable circuit configuration for potential-free signal transmission.
In industrial power electronics and systems engineering, for example, the control circuits and the power circuits often have to be DC-isolated from one another. The dictates of operation mean that the control circuits are subject to very great disturbances/interferences that lead to the malfunctioning or to the failure of the electrical system. The disturbances result from rapidly changing voltages and currents in the power circuit. In this way, very strong, rapidly changing electric (dU/dt) and magnetic (d"PHgr"/dt) fields arise which permeate the control circuits and influence them. In this case, optocouplers or pulse transformers are usually used for DC isolation. In the event of very high-frequency changes in electric fields, displacement currents are impressed through parasitic coupling capacitances. The currents can lead to malfunctions of optocouplers or pulse transformers. Furthermore, strong magnetic fields, especially in the transformer windings, can additionally induce undesired interference voltages which likewise cause faults. Furthermore, optocouplers have the disadvantage of a high current consumption. Moreover, on account of their considerable external dimensions, both optocouplers and primarily pulse transformers are unsuitable or at least undesirable in many cases.
U.S. Pat. Nos. 6,262,600, 5,952,849 and 4,027,152 disclose transformer configurations that can be at least partly integrated in a semiconductor body. However, they require a high outlay on circuitry.
This is because the operating range of a transformer is restricted on account of parasitic effects at high and relatively low frequencies. Each transformer accordingly behaves like a bandpass filter. In this case, the operating frequency range depends to a very great extent on the construction and on the size of the transformer. The known planar transformers that are applied on the surface of a semiconductor chip have spiral windings and these windings, for their part, have a relatively high conductor track resistance. Therefore, the ratio of the self-inductance L of the winding to the resistance R thereof is unfavorable. The ratio of the two produces the time constant of the winding Tp=L/R. The time constant restricts the operating frequency of the transformer particularly at relatively low frequencies. By way of example, for planar transformers having external diameters of up to 500 xcexcm, produced in a standard technology, the time constant lies in the range of 1-5 ns, that is to say that the minimum operating frequency (xe2x88x923 dB) is 35 MHz to 165 MHz.
In order to transmit items of information by a transformer of this type, the signal duration must be of the order of magnitude of the time constant. However, this requires complicated high-frequency circuits in order to be able to generate the short pulses, because in the event of longer pulses the winding attains saturation, so that a transmission of information or energy is no longer possible.
It is accordingly an object of the invention to provide an integratable circuit configuration for potential-free signal transmission that overcomes the above-mentioned disadvantages of the prior art devices of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for potential-free signal transmission. The circuit configuration contains a transformer having two windings magnetically coupled to one another. The two windings include a primary winding and a secondary winding. A drive circuit is connected upstream of the primary winding and converts edges of a logical input signal into primary-side pulses corresponding to the logical input signal. Each of the primary-side pulses in the primary winding generates in the secondary winding secondary pulses corresponding to the edges of the logical input signal. A selection circuit is connected up to the secondary winding. The selection circuit is driven by the secondary pulses and separates the secondary pulses according to a respective assignment to an edge of the logical input signal. A latching circuit is connected downstream of the selection circuit, the latching circuit compares separate ones of the secondary pulses with one another and prevents a forwarding of the secondary pulses in an event of separate ones of the secondary pulses occurring simultaneously and/or in an event of the secondary pulses occurring in short-time succession. A storage element is connected to the latching circuit. The storage element is set by the secondary pulses of a first polarity, is reset by the secondary pulses of a second polarity, and generates an output signal.
The transformer configuration according to the invention has the advantage that, in addition to the small dimensions, only a low outlay is required, only low power consumption exists, and the susceptibility to interference is low.
This is achieved by the circuit configuration having a transformer with two windings that are magnetically coupled to one another and of which one is provided as the primary winding and the other as the secondary winding. In this case, a drive circuit is connected upstream of the primary winding and converts edges of a logical input signal into primary-side pulses corresponding to the input signal. Each of the primary pulses in the primary winding generates secondary pulses that can be assigned to the edges of the input signal in the secondary winding. A selection circuit is connected up to the secondary winding, which selection circuit is driven by the secondary pulses and separates the secondary pulses according to a respective assignment to the edge of the input signal. Finally, a latching circuit is provided, which is downstream of the selection circuit, compares separate secondary pulses with one another and, in the event of separate secondary pulses occurring simultaneously and/or in the event of secondary pulses occurring in short-time succession, prevents a forwarding of the secondary pulses to a storage element which is set by secondary pulses of one polarity and is reset by secondary pulses of the other polarity and carries an output signal.
The duration of the pulses may be dimensioned in such a way that the transformer is operated in saturation.
During the linear operation of the transformer as in the prior art, the saturation state is prevented from being reached because no voltage is induced in the secondary winding. In the case of the customary signal transmission without saturation of the transformer, the pulse width of the output voltage is equal to the pulse width of the input voltage. The voltage waveform at the input and at the output is also approximately identical. The two signals are temporally coincident. In the case of the development of the invention, the problematic property of the very short time constant Tp=L/R of the primary winding is utilized to the effect that, with each voltage pulse on the primary winding, two very short pulses of the opposite polarity and following very shortly one after another are induced in the secondary winding. The polarity of the output pulses is unambiguously assigned to the polarity of the edges of the input voltage, so that only a simple drive circuit and a simple evaluation circuit are necessary.
The above development of the invention is thus based on taking account of the properties of the planar transformer in a circuit that does not utilize the linear operating range of the transformer. This is achieved in particular by virtue of the fact that the maximum operating frequency of the electronic circuit that drives the transformer lies below the operating frequency range of the transformer. The drive and evaluation devices allow a faithful re-establishment of the information despite the different operating frequencies. Consequently, it is not necessary to use expensive high-frequency technology for the circuit in order to utilize the integrated planar transformer for the DC isolation of the signals.
In a development of the invention, a primary refresh pulse may be generated after each primary pulse generated, which refresh pulse, in the case of the circuit configuration not responding after the first pulse, then leads to a reliable response at the second attempt.
The selection circuit may have two comparators, to which, on the one hand, a reference potential is in each case applied, and which, on the other hand, are driven with the secondary pulses in an inverse manner with respect to one another.
In the case of the above-mentioned circuit configuration, two transformers may also be provided, of which two are provided as primary windings and two as secondary windings, each of the primary windings being magnetically coupled to a respective one of the secondary windings.
In this case, the drive circuit may be configured for driving the two primary windings, the drive circuit driving the two primary windings in an inverse manner with respect to one another or, in the event of a state change of the input signal occurring, driving one or the other primary winding depending on the direction of the state change.
Furthermore, the selection circuit may have four comparators, to which a reference potential is in each case applied, and which, are driven with the secondary pulses in pairs in an inverse manner with respect to one another. The outputs of the comparators of one pair are combined with the outputs of the other pair via a respective AND gate (or corresponding logic combinations).
The latching circuit may have two controllable switches, which are in each case connected downstream of the signal shapers (comparators), and are controlled by a coincidence circuit.
In this case, the coincidence circuit may determine the coincidence of signals occurring in the secondary windings and, in the event of coincident signals being present on both secondary windings, identifies an erroneous transmission and accordingly prevents the forwarding of the secondary pulses. As an alternative, it may determine the coincidence of secondary signals that are separated after the secondary windings and, in the event of coincident signals being present, correspondingly identifies an erroneous transmission.
The coincidence circuit preferably contains an AND gate or two timing elements cross-coupled to the switches for determining the coincidence.
In a refinement of the invention, the (respective) primary and secondary windings may be formed in different planes in the direction of the winding axes. Furthermore, the windings are preferably formed in a spiral shape or fashion.
Finally, the circuit configuration is partly or preferably completely integrated into a semiconductor body.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integratable circuit configuration for potential-free signal transmission, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.